Wirebonding Based 3-D SiC IC Stacks for High Temperature Applications
Author:
Affiliation:
1. University of Idaho,Department of Electrical and Computer Engineering,Moscow,Idaho,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816592.pdf?arnumber=9816592
Reference7 articles.
1. Application of Alumina-Based Ceramic Paste for High-Temperature Electronics Packaging;nasiri;Journal of Electronic Packaging,2020
2. Operational Testing of 4H-SiC JFET ICs for 60 Days Directly Exposed to Venus Surface Atmospheric Conditions
3. Sixty Earth-Day Test of a Prototype Pt/HTCC Alumina Package in a Simulated Venus Environment
4. High-Temperature Electronics Packaging for Simulated Venus Condition
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1. Flip-Chip Bonding for SiC Integrated Circuits With Gold Stud Bumps for High Temperature Up To 600 °C Applications;IEEE Transactions on Components, Packaging and Manufacturing Technology;2024-04
2. Flip-Chip Bonding of SiC Chips onto Alumina Substrate for High-Temperature Applications;2024 IEEE Workshop on Microelectronics and Electron Devices (WMED);2024-03-29
3. Metal-to-Metal Flip-Chip Bonding for High-Temperature 3D SiC IC Integration and Packaging;2023 IEEE Workshop on Microelectronics and Electron Devices (WMED);2023-03
4. GaN Ring Oscillators Operational at 500 °C Based on a GaN-on-Si Platform;IEEE Electron Device Letters;2022-11
5. 3-D Stacking of SiC Integrated Circuit Chips With Gold Wire Bonded Interconnects for Long-Duration High-Temperature Applications;IEEE Transactions on Components, Packaging and Manufacturing Technology;2022-10
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