A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8334884/8350884/08351396.pdf?arnumber=8351396
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design Methods of Integrated Circuits, Working Under Non-standard Operating Conditions;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31
2. Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05
3. A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range;Electronics;2023-06-16
4. A Wide-Range Four-Phase All-Digital DLL with De-Skew Circuit;Electronics;2023-03-29
5. A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL;Circuits, Systems, and Signal Processing;2019-08-08
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