A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8334884/8350884/08350899.pdf?arnumber=8350899
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor;Microelectronics Journal;2024-08
2. A Low Power Cyclic ADC Architecture using Reference Scaling Technique;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. Forward-backward Transliteration of Punjabi Gurmukhi Script Using N-gram Language Model;ACM Transactions on Asian and Low-Resource Language Information Processing;2022-12-27
4. A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. A Multiplying Digital to Analog Converter Insensitive to Component Mismatch;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
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