A 12-bit 2.5-bit/phase two-stage cyclic ADC with phase scaling and low-power Sub-ADC for CMOS image sensor
Author:
Funder
NSAF Joint Fund
Publisher
Elsevier BV
Reference18 articles.
1. 11-bit column-parallel single-slope ADC with first-step half-reference ramping scheme for high-speed CMOS image sensors;Kim;IEEE J. Solid State Circ.,2021
2. 2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor;Wang;Microelectron. J.,2023
3. A delta-readout scheme for low-power CMOS image sensors with multi-column-parallel SAR ADCs;Kim;IEEE J. Solid State Circ.,2016
4. A low-noise high intrascene dynamic range CMOS image sensor with a 13 to 19b variable-resolution column-parallel folding-integration/cyclic ADC;Seo;IEEE J. Solid State Circ.,2011
5. A 1.1-μm 33-mpixel 240-fps 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-SAR analog-to-digital converters;Arai;IEEE Trans. Electron. Dev.,2017
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