Fault Tolerance Analysis of NoC Architectures-Reference-Cited by-同舟云学术

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Fault Tolerance Analysis of NoC Architectures

Published:2007-05 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE International Symposium on Circuits and Systems
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Author:

Lehtonen Teijo,Liljeberg Pasi,Plosila Juha

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4252534/4252535/04252646.pdf?arnumber=4252646

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-performance and energy-efficient fault-tolerance core mapping in NoC;Sustainable Computing: Informatics and Systems;2017-12

2. A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-11

3. A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core;2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2016-07

4. A Performance Enhanced Dual-switch Network-on-chip Architecture;IPSJ Transactions on System LSI Design Methodology;2015

5. Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE);International Journal of Engineering;2014-04

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