Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications
Author:
Affiliation:
1. Department of Electrical Engineering and Computer Science, Daegu Gyeongbuk Institute of Science and Technology, Daegu, South Korea
Funder
DGIST Start-Up Fund Program of the Ministry of Science and ICT
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Medicine
Link
http://xplorestaging.ieee.org/ielx7/8784029/9684754/09827577.pdf?arnumber=9827577
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1. A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
2. A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology
3. A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS
4. A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
5. A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
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