A 6T-SRAM-Based Computing-In-Memory Architecture using 22nm FD-SOI Device
Author:
Affiliation:
1. University of Electronic Science and Technology of China,Dept. of Key Laboratory of Thin Solid Films and Integrated Devices,Chengdu,China
2. Deepcreatic technologies Lt,Chengdu,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10150429/10151454/10151524.pdf?arnumber=10151524
Reference17 articles.
1. 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
2. Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications
3. A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
4. 10T SRAM computing-in-memory macros for binary and multibit MAC operation of DNN edge processors;kim;IEEE Access,2021
5. A Novel Voltage-Accumulation Vector-Matrix Multiplication Architecture Using Resistor-shunted Floating Gate Flash Memory Device for Low-power and High-density Neural Network Applications
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