Graph Representation and Embedding for Semiconductor Manufacturing Fab States
Author:
Affiliation:
1. Karlsruhe Institute of Technology (KIT), Institute for Material Handling and Logistics (IFL),Karlsruhe,GERMANY,76131
2. Robert Bosch GmbH,Reutlingen,GERMANY,72762
3. D-SIMLAB Technologies Pte Ltd,Singapore,SINGAPORE,609434
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10015196/10015230/10015297.pdf?arnumber=10015297
Reference36 articles.
1. An Integration of Static and Dynamic Capacity Planning for a Ramping Fab
2. Challenges Associated with Realization of Lot Level Fab Out Forecast in a Giga Wafer Fabrication Plant
3. Harmonizing operations management of key stakeholders in wafer fab using discrete event simulation
4. Implementation of a simulation-based short-term lot arrival forecast in a mature 200mm semiconductor FAB
5. Predicting multicellular function through multi-layer tissue networks
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2. Combining Time Series Data and Snapshot Data for Situation Aware Dispatching in Semiconductor Manufacturing;2023 Winter Simulation Conference (WSC);2023-12-10
3. Graph Representation Learning and Its Applications: A Survey;Sensors;2023-04-21
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