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Shot-Noise-Induced Failure in Nanoscale Flip-Flops Part II: Failure Rates in 10-nm Ultimate CMOS

  • Published:2012-03 Issue:3 Volume:59 Page:807-812
  • ISSN:0018-9383
  • Container-title:IEEE Transactions on Electron Devices
  • language:
  • Short-container-title:IEEE Trans. Electron Devices

Author:

Jannaty Pooya,Sabou Florian C.,Le Son T.,Donato Marco,Bahar R. Iris,Patterson William,Mundy Joseph,Zaslavsky Alexander

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM;IEEE Transactions on Device and Materials Reliability;2020-09

2. Thermal Noise-Induced Error Simulation Framework for Subthreshold CMOS SRAM;2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S);2019-10-14

3. A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-03

4. A fast simulator for the analysis of sub-threshold thermal noise transients;Proceedings of the 53rd Annual Design Automation Conference;2016-06-05

5. A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits;Proceedings of the 25th edition on Great Lakes Symposium on VLSI;2015-05-20
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