Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM-Reference-Cited by-同舟云学术

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Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM

Published:2020-09 Issue:3 Volume:20 Page:488-497
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Rezaei Elahe^ORCID,Donato Marco^ORCID,Patterson William R.^ORCID,Zaslavsky Alexander^ORCID,Bahar R. Iris^ORCID

Funder

National Science Foundation Grant through the CISE Directorate

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

https://ieeexplore.ieee.org/ielam/7298/9186371/9098936-aam.pdf

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Stochastic Nonlinear Dynamical Modelling of SRAM Bitcells in Retention Mode;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

2. Variability-Aware Noise-Induced Dynamic Instability of Ultra-Low-Voltage SRAM Bitcells;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27

3. Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-01

4. Predicting State Transitions in Autonomous Nonlinear Bistable Systems With Hidden Stochasticity;IEEE Control Systems Letters;2024

5. On noise-induced transient bit flips in subthreshold SRAM;Solid-State Electronics;2023-10

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