A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits-Reference-Cited by-同舟云学术

A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits

Published:2015-12 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Electron Devices Meeting (IEDM)
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Author:

van Dalen R.,Tuinhout H. P.,Stoutjesdijk M.,van Zwol J.,Zaal J. J. M.,Janssen J. H. J.,Swartjes F. H. M.,Bastiaansen P. A. M.,Lammers M. C.,Brusamarello L.,Stekelenburg M.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7402013/7409598/07409646.pdf?arnumber=7409646

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