Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND-Reference-Cited by-同舟云学术

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Experimental and theoretical verification of channel conductivity degradation due to grain boundaries and defects in 3D NAND

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Subirats A.,Arreghini A.,Capogreco E.,Delhougne R.,Tan C.-L.,Hikavyy A.,Breuil L.,Degraeve R.,Putcha V.,Van den bosch G.,Linten D.,Furnemont A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268433.pdf?arnumber=8268433

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Discrete-Trap Effects on 3-D NAND Variability – Part II: Random Telegraph Noise;IEEE Journal of the Electron Devices Society;2024

2. Discrete-Trap Effects on 3-D NAND Variability – Part I: Threshold Voltage;IEEE Journal of the Electron Devices Society;2024

3. Insights into device and material origins and physical mechanisms behind cross temperature in 3D NAND;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03

4. Channel Thickness and Grain Size Engineering for Improvement of Variability and Performance in 3-D NAND Flash Memory;IEEE Transactions on Electron Devices;2022-07

5. Variability and disturb sources in ferroelectric 3D NANDs and comparison to Charge-Trap equivalents;2022 IEEE International Memory Workshop (IMW);2022-05

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