The impact of sequential-3D integration on semiconductor scaling roadmap-Reference-Cited by-同舟云学术

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The impact of sequential-3D integration on semiconductor scaling roadmap

Published:2017-12 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Electron Devices Meeting (IEDM)
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Author:

Mallik A.,Vandooren A.,Witters L.,Walke A.,Franco J.,Sherazi Y.,Weckx P.,Yakimets D.,Bardon M.,Parvais B.,Debacker P.,Ku B. W.,Lim S. K.,Mocuta A.,Mocuta D.,Ryckaert J.,Collaert N.,Raghavan P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268483.pdf?arnumber=8268483

Cited by 27 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. System technology co-optimization for advanced integration;Nature Reviews Electrical Engineering;2024-09-02

2. Unified multifunctional-reconfigurable architecture for device-circuit co-design;Microelectronics Journal;2024-09

3. Characterization and Advanced Modeling of Dielectric Defects in Low-Thermal Budget RMG MOSFETs Using 1/f Noise Analysis;IEEE Transactions on Electron Devices;2024-03

4. Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

5. Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs ^*;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

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