Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits-Reference-Cited by-同舟云学术

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Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits

Published:2018-12 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Electron Devices Meeting (IEDM)
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Author:

Yang Chih-Chao,Hsieh Tung-Ying,Huang Po-Tsang,Chen Kuan-Neng,Wu Wan-Chi,Chen Shih-Wei,Chang Chia-He,Shen Chang-Hong,Shieh Jia-Min,Hu Chenming,Wu Meng-Chyi,Yeh Wen-Kuan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8601505/8614478/08614708.pdf?arnumber=8614708

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-density integration of uniform sub-22 nm silicon nanowires for transparent thin film transistors on glass;Applied Surface Science;2025-01

2. Application of Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique on Different Oriented Wafers for Monolithic 3DIC Integration;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

3. New structure transistors for advanced technology node CMOS ICs;National Science Review;2024-01-05

4. Nanowire FETs With Nearly Single-Crystalline Si Channels by NiSi₂-Seed Initiated Lateral Epitaxial Crystallization (SILEC);IEEE Electron Device Letters;2024-01

5. Application of Pulsed Green Laser Activation to Top-Tier MOSFET Fabrication for Monolithic 3-D Integration;IEEE Transactions on Electron Devices;2024-01

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