Lateral charge migration suppression of 3D-NAND flash by vth nearing for near data computing
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/8255107/8268301/08268420.pdf?arnumber=8268420
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Numerical Simulation of Trapped Hole Lateral Migration and Induced Threshold Voltage Retention Loss in a SONOS Flash Memory;IEEE Transactions on Device and Materials Reliability;2023-03
2. Decomposition of Vertical and Lateral Charge Loss in Long-term Retention of 3-D NAND Flash Memory;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
3. TCSE: A Target Cell States Elimination Coding Strategy for Highly Reliable Data Storage Based on 3-D nand Flash Memory;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
4. A low-complexity coding method for mitigating retention errors and read-disturb errors in TLC NAND flash memory;Proceedings of the Conference on Research in Adaptive and Convergent Systems;2022-10-03
5. Pulse optimization and device engineering of 3D charge-trap flash for synaptic operation;Journal of Applied Physics;2022-09-21
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