A Low Noise High PSR LDO Based on N-type Flipped Voltage Follower
Author:
Affiliation:
1. Zhejiang University,School of Micro-Nano Electronics,Hangzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9958944/9959090/09959400.pdf?arnumber=9959400
Reference7 articles.
1. High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique
2. A 4-GHz clock system for a high-performance system-on-a-chip design
3. 18.1 A -105dBc THD+N (-114dBc HD2) at 2.8VPP Swing and 120dB DR Audio Decoder with Sample-and-Hold Noise Filtering and Poly Resistor Linearization Schemes
4. A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range
5. A 0.5–1 V, −68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS
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1. A high power efficiency high power supply rejection LDO with fast-transient response;2024-08-27
2. A fast-transient dual loop LDO with high PSR;IEICE Electronics Express;2024-05-10
3. A low power LDO with high PSR over a wide frequency range based on an impedance attenuation buffer;IEICE Electronics Express;2024-03-25
4. Design of a Low-Noise Low Dropout Regulator for CMOS Pixel Sensors;IEEE Access;2024
5. An External Cap-Less LDO with Low Noise and High Power Supply Rejection;2023 IEEE MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP);2023-11-13
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