Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs
Author:
Affiliation:
1. University College Dublin,School of Electrical and Electronic Engineering,Dublin,Ireland
Funder
Science Foundation Ireland
Enterprise Ireland
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198146.pdf?arnumber=10198146
Reference13 articles.
1. Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs
2. Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities
3. A random pulse modulation approach to modeling the flicker and white noise of the charge pump of a fractional‐N frequency synthesizer
4. Jitter Minimization in Digital PLLs with Mid-Rise TDCs
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1. Comparison of DTC Segmentation Methods in Fractional-N Frequency Synthesizers;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
3. Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
4. MMSE Estimator for Linearized Analysis and SNR of ADCs Tested with Sinusoidal Inputs;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18
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