Jitter Minimization in Digital PLLs with Mid-Rise TDCs
Author:
Funder
Science Foundation Ireland
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/9014409/08946565.pdf?arnumber=8946565
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Comparison of DTC-Related Spurs in Fractional-N Digital PLLs with MASH-and-ENOP-based Divider Controllers;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04
2. Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12
3. A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
4. Linearized Analysis of Mid-Rise TDCs for Integer-N and Fractional-N Digital PLLs;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
5. Comparative Study of Linearized Analysis Frameworks for Mid-Rise TDCs;2023 21st IEEE Interregional NEWCAS Conference (NEWCAS);2023-06-26
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