A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity
Author:
Affiliation:
1. Politecnico di Milano,Milan,Italy
2. Infineon Technologies AG,Villach,Austria
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198057.pdf?arnumber=10198057
Reference17 articles.
1. A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
2. 3.1 A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
3. A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy;ni;IEEE Transactions on Circuits and Systems I Regular Papers,2021
4. A 12 bit 8 GS/s Time-Interleaved SAR ADC in 28nm CMOS
5. A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
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1. A Wideband Input Buffer Based on Cascade Complementary Source Follower;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05
2. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024
3. A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity;IEICE Electronics Express;2024
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