Error Analysis for Fused Floating-point Square-root and Division based on Goldschmidt Algorithm
Author:
Affiliation:
1. ShanghaiTech University,School of Information Science and Technology,Shanghai,China
2. UESTC,School of Integrated Circuit Science and Engineering,Chengdu,China
Funder
Shanghai Rising-Star Program
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10198027/10198028/10198192.pdf?arnumber=10198192
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1. An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU
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3. Floating-point division and square root implementation using a Taylor-series expansion algorithm
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5. CMOS floating-point unit for the S/390 Parallel Enterprise Server G4
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Low-Latency High-Throughput Multi-Precision Fused Floating-Point Division and Square-Root Unit Design;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
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