Speed and power scaling of SRAM's-Reference-Cited by-同舟云学术

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Speed and power scaling of SRAM's

Published:2000-02 Issue:2 Volume:35 Page:175-185
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Amrutur B.S.,Horowitz M.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/17827/00823443.pdf?arnumber=823443

Cited by 71 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ReHarvest: An ADC Resource-Harvesting Crossbar Architecture for ReRAM-Based DNN Accelerators;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. Static Noise Margin Evaluation of Planar CMOS and FinFET based Static Random Access Memory for Nanoscaled Technology;2024 5th International Conference on Recent Trends in Computer Science and Technology (ICRTCST);2024-04-09

3. A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM;IEICE Electronics Express;2023-12-25

4. A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

5. Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-08

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