Latency Insensitive Design Styles for FPGAs-Reference-Cited by-同舟云学术

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Latency Insensitive Design Styles for FPGAs

Published:2018-08 Issue: Volume: Page:
ISSN:
Container-title:2018 28th International Conference on Field Programmable Logic and Applications (FPL)
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Author:

Abbas Mustafa,Betz Vaughn

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8529150/8530786/08533523.pdf?arnumber=8533523

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design;ACM Transactions on Reconfigurable Technology and Systems;2023-12-05

2. HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11

3. Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics;2023 IEEE International Conference on Cluster Computing (CLUSTER);2023-10-31

4. Placement Optimization for NoC-Enhanced FPGAs;2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM);2023-05

5. A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA;ACM Transactions on Reconfigurable Technology and Systems;2023-01-18

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