A Pre-Silicon Physical Design Study Towards Mitigating EMSCA on Cryptographic ICs
Author:
Affiliation:
1. Georgia Institute of Technology,Department of ECE,Atlanta,Georgia,USA
2. Georgia Tech Research Institute,Atlanta,Georgia,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10545333/10545347/10545400.pdf?arnumber=10545400
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1. MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm
2. A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
3. Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
4. Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering
5. Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator;Kar,2018
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