Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects-Reference-Cited by-同舟云学术

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Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

Published:2011-09 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE Recent Advances in Intelligent Computational Systems
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Author:

Verma K. G.,Singh Raghuvir,Kaushik B. K.,Majumder Manoj Kumar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/6059528/6069258/06069381.pdf?arnumber=6069381

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Machine Learning Techniques for Modeling and Performance Analysis of Interconnects;IEEE Open Journal of Nanotechnology;2021

2. Stochastic Buffering for Bundled SWCNT Interconnects Considering Unidimensional Fabrication Variation;IEEE Transactions on Emerging Topics in Computing;2019-10-01

3. Effect of Line Parasitic Variations on Delay and Energy of Global On-Chip VLSI Interconnects in DSM Technology;Proceedings of 2nd International Conference on Micro-Electronics, Electromagnetics and Telecommunications;2017-09-07

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