Author:
Venkataiah C.,Satyaprasad K.,Jaya Chandra Prasad T.
Reference15 articles.
1. B. K. Kaushik and S. Sarkar, “Crosstalk Analysis for a CMOS- Gate- Driven Coupled Interconnects” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1150–1154, Jun. 2008.
2. K. G. Verma, Raghuvir Singh, B. K. Kaushik and Manoj Kumar Majumder “Propagation Delay Deviations due to Process Induced Line Parasitic Variations in Global VLSI Interconnects” IEEE Conference on Recent Advances in Intelligent Computational Systems (RAICS), 2011.
3. C. Venkataiah, M. Tejaswi “A Comparative Study of Interconnect Circuit Techniques for Energy Efficient on-Chip Interconnects” International Journal of Computer Applications (0975 – 8887) Volume 109 – No. 4, January 2015.
4. International Technology Roadmap for Semiconductors, 2013. [Online] Available: http://public.itrs.net/ .
5. S. Borkar, T. Kamik, S. Narendra, J. Tschanz, A. Keshavarzi and V. De, “Parameter variations and impact on circuits and micro architecture,” in Proc. Design Automation Conference (DAC), pp. 338–342, 2003.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献