A Proposal for Programmable Pattern Generator and its FPGA implementation-Reference-Cited by-同舟云学术

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A Proposal for Programmable Pattern Generator and its FPGA implementation

Published:2022-12-15 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
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Author:

Somanathan Geethu Remadevi¹,Bhakthavatchalu Ramesh¹

Affiliation:

1. Amrita Vishwa Vidyapeetham,Department of Electronics and Communication Engineering,Amritapuri,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10046417/10046432/10046457.pdf?arnumber=10046457

Reference16 articles.

1. An enhanced architecture for high performance BIST TPG

2. Modelling of Random Number Generator based on PUFs and LFSR for secret key generation

3. A low power pseudo-random BIST technique

4. A Novel SMT-Based Technique for LFSR Reseeding

5. LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Design of Integrated Circuit Auxiliary Testing Scheme Based on FPGA;2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE);2024-05-24

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