A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology-Reference-Cited by-同舟云学术

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A low-power high-speed two-stage dynamic comparator with a new offset cancellation technique in 90 nm CMOS technology

Published:2020-08-04 Issue: Volume: Page:
ISSN:
Container-title:2020 28th Iranian Conference on Electrical Engineering (ICEE)
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Author:

Ghasemi Razieh,Karami Mohammad Azim

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9260489/9260590/09260623.pdf?arnumber=9260623

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Examining and Evaluating Comparator Circuit Performance Experimentally at Various Technology Nodes;2023 3rd International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2023-12-29

2. A dynamic power-efficient 4 GS/s CMOS comparator;AEU - International Journal of Electronics and Communications;2023-10

3. Design of Self-Calibration Comparator for 12-Bit SAR ADCs;Electronics;2023-05-18

4. 45nm CMOS Two-Stage Latched Comparator;2022 International Conference on Smart Systems and Power Management (IC2SPM);2022-11-10

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