1. Analysis of Optimization on Sparse Matrix Vector Multiplication Model Application in Digital Signal Processing;2024 IEEE 3rd International Conference on Electrical Power and Energy Systems (ICEPES);2024-06-21
2. A shared compilation stack for distributed-memory parallelism in stencil DSLs;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2024-04-27
3. Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
4. Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA;Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis;2023-11-12
5. Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs;2023 33rd International Conference on Field-Programmable Logic and Applications (FPL);2023-09-04