Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs-Reference-Cited by-同舟云学术

Fortran High-Level Synthesis: Reducing the Barriers to Accelerating HPC Codes on FPGAs

Published:2023-09-04 Issue: Volume: Page:
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Container-title:2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)
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Author:

Rodriguez-Canal Gabriel¹,Brown Nick¹,Dykes Tim²,Jones Jess²,Haus Utz-Uwe²

Affiliation:

1. The University of Edinburgh,EPCC

2. Hewlett Packard Enterprise,HPC/AI EMEA Research Lab

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10296174/10296123/10296353.pdf?arnumber=10296353

Reference19 articles.

1. LLVM and Clang: Next generation compiler technology;lattner;The BSD Conference,0

2. Automatic Pipelining and Vectorization of Scientific Code for FPGAs

3. A single-source C++20 HLS flow for function evaluation on FPGA and beyond.

4. The State of Fortran

5. Productivity, portability, performance:data-centric Python;ziogas;Proceedings of the International Conference for High Performance Computing Networking Storage and Analysis,0

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