M*N Booth encoded multiplier generator using optimized Wallace trees

Author:

Fadavi-Ardekani J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 52 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Two-Speed,Radix-4, Parallel-Parallel Multiplier;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

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3. A STT-Assisted SOT MRAM-Based In-Memory Booth Multiplier for Neural Network Applications;IEEE Transactions on Nanotechnology;2024

4. Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier;Electronics;2023-07-25

5. Design of Modified Booth’s Encoder Using SPST technique;International Journal of Electrical Engineering and Computer Science;2023-07-18

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