Approximate Booth Multipliers using Compressors and Counter
Author:
Affiliation:
1. KIT-Kalaignarkarunanidhi Institute of technology,Department of Electronics and Communication Engineering,Coimbatore,641402
2. KIT-Kalaignarkarunanidhi Institute of technology,M. E. - VLSI Design,Coimbatore,641402
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10133935/10133936/10134198.pdf?arnumber=10134198
Reference15 articles.
1. General data-path organization of a MAC unit for VLSI implementation of DSP processors
2. A Suggestion for a Fast Multiplier
3. A Simple High-Speed Multiplier Design
4. Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error
5. Optimal circuits for parallel multipliers
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