Analysis and Design of Low Area and Highly Energy Efficient Hybrid Adder for Signal Processing Applications
Author:
Affiliation:
1. KIT-Kalaignarkarunanidhi Institute of Technology,Coimbatore,Tamilnadu,India
2. Sri Ramakrishna Engineering College,Coimbatore,Tamilnadu,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10009016/10009051/10009110.pdf?arnumber=10009110
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5. A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application
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