Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs-Reference-Cited by-同舟云学术

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Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs

Published:2023-05-10 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International 3D Systems Integration Conference (3DIC)
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Author:

Naeim Mohamed¹,Yang Hanqi¹,Chen Pinhong¹,Bao Rong¹,Dekeyser Antoine¹,Sisto Giuliano²,Brunion Moritz²,Chen Rongmei²,Van der Plas Geert²,Beyne Eric²,Milojevic Dragomir²

Affiliation:

1. Cadence Design System,San Jose,USA

2. IMEC,Heverlee,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10154896/10154899/10155075.pdf?arnumber=10155075

Reference6 articles.

1. Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications

2. Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route

3. OpenPiton

4. Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs

5. The 3-D Interconnect Technology Landscape

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

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