Author:
San Martin R.,Knight J.P.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
16 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Logic Synthesis;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
2. A Sat Based Scheduling Technique for Peak Power Minimization;Procedia Computer Science;2015
3. A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2013-02
4. Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis;20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07);2007-01
5. ILP models for simultaneous energy and transient power minimization during behavioral synthesis;ACM Transactions on Design Automation of Electronic Systems;2006-01