Author:
Tao Yong-Peng,Hu Wei-Ping
Cited by
9 articles.
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1. Cache Memory Design for Single Bit Architecture with Different Sense燗mplifiers;Computers, Materials & Continua;2022
2. High-Performance and Low-Voltage Current Sense-Amplifier Using GAA-CNTFET with Different Chirality and Channel;Research and Education: Traditions and Innovations;2022
3. Cache Memory Architecture for Core Processor;Proceedings of International Conference on Advanced Computing Applications;2021-11-24
4. Low-Power SRAM Memory Architecture for IoT Systems;Recent Advances in Manufacturing, Automation, Design and Energy Technologies;2021-10-12
5. Low Power Single-Bit Cache Memory Architecture;IOP Conference Series: Materials Science and Engineering;2021-04-01