A 64-bit carry look ahead adder using pass transistor BiCMOS gates

Author:

Ueda K.,Suzuki H.,Suda K.,Shinohara H.,Mashiko K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Two proposed BiCMOS inverters with enhanced performance;Ain Shams Engineering Journal;2024-01

2. Design of Various Low Power and Highspeed Full Adder Designs using 45nm Cmos Technology;International Journal of Innovative Technology and Exploring Engineering;2022-04-30

3. Performance Comparison of 64-bit Carry Look-Ahead Adders Using 32nm CMOS Technology;Materials Today: Proceedings;2017

4. Signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits;IEE Proceedings - Circuits, Devices and Systems;2006

5. A parallel back-propagation adder structure;International Journal of Electronics;1998-09

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