Suppressing Threshold Voltage Drift in Sub-2 nm In<sub>2</sub>O<sub>3</sub> Transistors With Improved Thermal Stability-Reference-Cited by-同舟云学术

Suppressing Threshold Voltage Drift in Sub-2 nm In₂O₃ Transistors With Improved Thermal Stability

Published:2024-01 Issue:1 Volume:45 Page:60-63
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Lin Kris K. H.¹^ORCID,Teng Li-Cheng¹^ORCID,Weng Tzu-Ting¹,Lin Tzu-Jie¹,Lin Jian-Cun¹,Wang Shin-Yuan¹^ORCID,Ho Po-Hsun²,Woon Wei-Yen²,Kei Chi-Chung³,Chou Tsung-Te³^ORCID,Chien Chao-Hsin¹,Lien Der-Hsien¹^ORCID

Affiliation:

1. Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, Taiwan

2. Taiwan Semiconductor Manufacturing Company, Hsinchu, Taiwan

3. National Applied Research Laboratories, Taiwan Instrument Research Institute, Hsinchu, Taiwan

Funder

National Science and Technology Council

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/55/10376160/10330598.pdf?arnumber=10330598

Reference27 articles.

1. Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration

2. Monolithic Heterogeneous Integration of BEOL Power Gating Transistors of Carbon Nanotube Networks with FEOL Si Ring Oscillator Circuits

3. Demonstration of Vertically-stacked CVD Monolayer Channels: MoS₂ Nanosheets GAA-FET with I_on>700 µA/µm and MoS2/WSe2 CFET

4. Monolithic 3D Integration of Vertically Stacked CMOS Devices and Circuits with High-Mobility Atomic-Layer-Deposited In₂O₃ n-FET and Polycrystalline Si p-FET: Achieving Large Noise Margin and High Voltage Gain of 134 V/V

5. Bandgap Extraction at 10 K to Enable Leakage Control in Carbon Nanotube MOSFETs

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