Author:
Simatic Jean,Cherkaoui Abdelkarim,Bertrand Francois,Bastos Rodrigo Possamai,Fesquet Laurent
Cited by
6 articles.
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1. An Efficient Design Flow for Iterative Asynchronous Bundled-Data Circuits on FPGA;2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV);2024-06-06
2. Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-07
3. From High-Level Synthesis to Bundled-Data Circuits;Lecture Notes in Computer Science;2020
4. On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-08
5. Comparison of Synchronous and Asynchronous FIR Filter Architectures;2019 5th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP);2019-05