From High-Level Synthesis to Bundled-Data Circuits-Reference-Cited by-同舟云学术

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From High-Level Synthesis to Bundled-Data Circuits

Published:2020 Issue: Volume: Page:200-212
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Decoudu Yoan,Simatic Jean,Morin-Allory Katell,Fesquet Laurent

Publisher

Springer International Publishing

Link

https://link.springer.com/content/pdf/10.1007/978-3-030-60939-9_14

Reference21 articles.

1. Bardsley, A.: Balsa: an asynchronous circuit synthesis system. Master’s thesis, University of Manchester (1998)

2. Chang, K.L., Chang, J., Gwee, B.H., Chong, K.S.: Synchronous-logic and asynchronous-logic 8051 microcontroller cores for realizing the Internet of Things: a comparative study on dynamic voltage scaling and variation effects. IEEE J. Emerg. Sel. Top. Circuits Syst. 3(1), 23–34 (2013)

3. Chu, T.A.: On the models for designing VLSI asynchronous digital systems. Integr. VLSI J. 4(2), 99–113 (1986)

4. Coussy, P., Gajski, D., Meredith, M., Takach, A.: An introduction to high-level synthesis. IEEE Des. Test Comput. 26(4), 8–17 (2009)

5. Garcia, K., Oliveira, D.L., d’Amore, R., Faria, L.A., Oliveira, J.L.V.: FPGA implementation of optimized XBM specifications by transformation for AFSMs. In: International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1–6 (2016)

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A High-Level Design Flow for Locally Body Biased Asynchronous Circuits;2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC);2021-10-04

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