Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs-Reference-Cited by-同舟云学术

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Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs

Published:2019-09 Issue:3 Volume:11 Page:93-96
ISSN:1943-0663
Container-title:IEEE Embedded Systems Letters
language:
Short-container-title:IEEE Embedded Syst. Lett.

Author:

Fuhr Gereon^ORCID,Hamurcu Seyit Halil,Pala Diego,Grass Thomas,Leupers Rainer,Ascheid Gerd,Eusse Juan Fernando

Funder

EM-RAM Project within the research program KMU-Innovativ

Bundesministerium für Bildung und Forschung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Computer Science,Control and Systems Engineering

Link

http://xplorestaging.ieee.org/ielx7/4563995/8818469/08653494.pdf?arnumber=8653494

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Assessment of Radiation Dosage to the Hippocampi during Treatment of Multiple Brain Metastases Using Gamma Knife Therapy;Medicina;2024-01-31

2. A CPU-FPGA Holistic Source-To-Source Compilation Approach for Partitioning and Optimizing C/C++ Applications;2023 32nd International Conference on Parallel Architectures and Compilation Techniques (PACT);2023-10-21

3. Matching Linear Algebra and Tensor Code to Specialized Hardware Accelerators;Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction;2023-02-17

4. Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators;IEEE Embedded Systems Letters;2021-09

5. An MPI-based MPSoC Platform in FPGA;IEEE Latin America Transactions;2021-04

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