Funder
Visvesvaraya Ph.D. Scheme, MeitY, Govt. of India
ZCU102 Board
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Computer Science,Control and Systems Engineering
Cited by
9 articles.
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1. Improved Hardware Accelerator for Object Detection;2024 International Conference on Signal Processing, Computation, Electronics, Power and Telecommunication (IConSCEPT);2024-07-04
2. UML-Based Design Flow for Systems with Neural Networks;2023 38th Conference on Design of Circuits and Integrated Systems (DCIS);2023-11-15
3. Sparse-DySta: Sparsity-Aware Dynamic and Static Scheduling for Sparse Multi-DNN Workloads;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
4. Performance Modeling and Estimation of a Configurable Output Stationary Neural Network Accelerator;2023 IEEE 35th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD);2023-10-17
5. Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective;IEEE Transactions on Computers;2023-05-01