High-speed parallel-prefix module 2/sup n/-1 adders-Reference-Cited by-同舟云学术

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High-speed parallel-prefix module 2/sup n/-1 adders

Published:2000-07 Issue:7 Volume:49 Page:673-680
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Kalampoukas L.,Nikolos D.,Efstathiou C.,Vergos H.T.,Kalamatianos J.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx5/12/18704/00863036.pdf?arnumber=863036

Cited by 99 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Comprehensive Approach and Analysis of Reverse Converters for a Class of Moduli Sets;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27

2. Modulo-(2^q − 3) Multiplication with Fully Modular Partial Product Generation and Reduction;2023 IEEE 30th Symposium on Computer Arithmetic (ARITH);2023-09-04

3. A Parallel Prefix Modulo-(2^q + 2^q−1 + 1) Adder via Diminished-1 Representation of Residues;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-08

4. Set the Domain for Using 3-moduli set {2^n-1, 2^n, 2^n +1};Signal and Data Processing;2023-06-01

5. Residue adder design for the modulo set {2ⁿ − 1, 2ⁿ, 2ⁿ⁺¹ − 1} and its application in DCT architecture for HEVC;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15

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