Residue adder design for the modulo set {2n − 1, 2n, 2n+1 − 1} and its application in DCT architecture for HEVC-Reference-Cited by-同舟云学术

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Residue adder design for the modulo set {2ⁿ − 1, 2ⁿ, 2ⁿ⁺¹ − 1} and its application in DCT architecture for HEVC

Published:2022-12-15 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
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Author:

Kopperundevi P.¹,Prakash M. Surya¹

Affiliation:

1. NIT Calicut,Dept. of Electronics and Communication Engineering,Calicut,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10046417/10046432/10046602.pdf?arnumber=10046602

Reference11 articles.

1. A Novel Algorithmic Approach for Efficient Realization of 2-D-DCT Architecture for HEVC

2. High Efficiency Video Coding (HEVC)

3. Area-efficient HEVC core transform using multi-sized and reusable DCT architectures

4. High-speed and reduced-area modular adder structures for RNS

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