Design Optimization of Multigate Bulk MOSFETs-Reference-Cited by-同舟云学术

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Design Optimization of Multigate Bulk MOSFETs

Published:2013-01 Issue:1 Volume:60 Page:28-33
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Ho Byron,Sun Xin,Shin Changhwan,Liu Tsu-Jae King

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/6387647/06365292.pdf?arnumber=6365292

Cited by 31 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The role of process and geometrical parameters of gate stack Inverted-T shape junction less FET at 20 nm technology node;Micro and Nanostructures;2024-09

2. Machine Learning-Based Device Modeling and Performance Optimization for FinFETs;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-04

3. Dual gate AlGaN/GaN MOS-HEMT biosensor for electrical detection of biomolecules-analytical model;Semiconductor Science and Technology;2023-02-01

4. Impact of ambient temperature and thermal resistance on device performance of junctionless silicon-nanotube FET;Nanotechnology;2022-05-25

5. Comparison of Drain Current Characteristics of Advanced MOSFET Structures - a Review;Silicon;2022-01-04

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