Author:
Basu Arkaprava,Hower Derek R.,Hill Mark D.,Swift Michael M.
Cited by
7 articles.
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1. PM3: Power Modeling and Power Management for Processing-in-Memory;2018 IEEE International Symposium on High Performance Computer Architecture (HPCA);2018-02
2. Probabilistic Directed Writebacks for Exclusive Caches;ACM SIGARCH Computer Architecture News;2016-07-12
3. Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures;Proceedings of the 2016 International Conference on Supercomputing;2016-06
4. Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches;2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID);2016-01
5. A Primer on Compression in the Memory Hierarchy;Synthesis Lectures on Computer Architecture;2015-12-18