A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction-Reference-Cited by-同舟云学术

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A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

Published:2013-02 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers
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Author:

Setterberg B.,Poulton K.,Ray S.,Huber D. J.,Abramzon V.,Steinbach G.,Keane J. P.,Wuppermann B.,Clayson M.,Martin M.,Pasha R.,Peeters E.,Jacobs A.,Demarsin F.,Al-Adnani A.,Brandt P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6480926/6487590/06487817.pdf?arnumber=6487817

Cited by 42 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

2. A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS;Microelectronics Journal;2024-04

3. A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

4. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024

5. A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12

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