A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS

Author:

Hsueh Kang-Wei,Chou Yu-Kai,Tu Yu-Hsuan,Chen Yi-Fu,Yang Ya-Lun,Li Hung-Sung

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. The Fully Differential Ring Amplifier with Wide Output Voltage Range Using Correlated Level Shifting Technique for The Pipelined ADCs;2024 International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC);2024-07-02

2. Advances in Analog-to-Digital Converters over the Last Decade;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2017

3. Recent Advances and Trends in High-Performance Embedded Data Converters;High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing;2014-07-24

4. A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique;Microelectronics Journal;2011-11

5. Low-Power Pipelined A/D Conversion;Analog Circuit Design;2011-09-04

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