A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS-Reference-Cited by-同舟云学术

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A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS

Published:2018-02 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE International Solid - State Circuits Conference - (ISSCC)
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Author:

Tang Liangxiao,Gai Weixin,Shi Linqi,Xiang Xiao,Sheng Kai,He Ai

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310210.pdf?arnumber=8310210

Cited by 41 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology;Microelectronics Journal;2024-09

2. A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

3. A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques;IEEE Journal of Solid-State Circuits;2024-08

4. A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation;IEICE Electronics Express;2024-04-10

5. A 50 Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation;IEICE ELECTRON EXPR;2024

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