12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications-Reference-Cited by-同舟云学术

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12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Clinton Michael,Cheng Hank,Liao HJ,Lee Robin,Wu Ching-Wei,Yang Johnny,Hsieh Hau-Tai,Wu Frank,Yang Jung-Ping,Katoch Atul,Achyuthan Arun,Mikan Donald,Sheffield Bryan,Chang Jonathan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870335.pdf?arnumber=7870335

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 3-nm FinFET 27.6-Mbit/mm² Single-Port 6T SRAM Enabling 0.48–1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking;IEEE Journal of Solid-State Circuits;2024-04

2. Design by Open Source Memory Compiler and its Potential;IEICE ESS Fundamentals Review;2024-04-01

3. A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

4. An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

5. On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond;Microelectronics Journal;2023-08

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