Design by Open Source Memory Compiler and its Potential
Author:
Affiliation:
1. Dept. of Information Systems Engineering, Faculty of Environmental Engineering, The University of Kitakyushu
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/essfr/17/4/17_265/_pdf
Reference14 articles.
1. 1) S.K. Vishvakarma, B.S. Reniwal, V. Sharma, C.B. Khuswah, and D. Dwivedi, “Nanoscale memory design for efficient computation: trends, challenges and opportunity,” Proc. 2015 International Symposium on Nanoelectronic and Information Systems (ISNIS), pp.29-34, Feb. 2015, doi: 10.1109/iNIS.2015.58.
2. 2) M. Clinton, H. Cheng, H.J. Liao, R. Lee, C.-W. Wu, J. Yang, H.-T. Hsieh, F. Wu, J.-P. Yang, and A. Katoch, “A low-power and high-performance 10 nm SRAM architecture for mobile applications,” Proc. 2017 International Solid-State Circuits Conference (ISSCC), pp.210-211, Feb. 2017, doi: 10.1109/ISSCC.2017.7870335.
3. 3) G. Prasad, D. Tandon, Isha, B.C. dra Mandi, and M. Ali, “Process variation analysis of 10T SRAM cell for low power, high speed cache memory for IoT applications,” Proc. 7th International Conference on Signal Processing and Integrated Networks (SPIN), pp.891-895, Feb. 2020, doi: 10.1109/SPIN48934.2020.9070999.
4. 4) V. Vashishtha, M. Vangala, P. Sharma, and L.T. Clark, “Robust 7-nm SRAM design on a predictive PDK,” Proc. 2017 International Symposium on Circuits and Systems (ISCAS), pp.1-4, May 2017, doi: 10.1109/ISCAS.2017.8050316.
5. 5) M.R. Guthaus, J.E. Stine, S. Ataei, B. Chen, B. Wu, and M. Sarwar, “OpenRAM: an open-source memory compiler,” Proc. the 35th International Conference on Computer-Aided Design (ICCAD), pp.1-6, Nov. 2016, doi: 10.1145/2966986.2980098.
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